There is a continuing push to produce smaller microelectronic devices with lower power consumption and faster switching speeds. With device miniaturization, however, comes a number of new design problems. In particular, as new technologies are implemented to produce smaller device components, there is a need to retain compatibility with other components still being produced by older technologies. Consider, for instance, efforts to scale-down microelectronic devices such as metal oxide semiconductor (MOS) transistors.
Scaling down the thickness of the transistor's gate dielectric advantageously produces a higher electric field in the channel for a given applied gate voltage, which in turn produces a higher on-state current. Ideally, when the transistor is biased to create channel inversion, the gate has sufficient numbers of dopants to allow the electric field lines to end at the interface between the gate and gate dielectric.
Unfortunately, gates comprising semiconductor material, such as doped polysilicon, are manufactured with a limited number of dopants at this interface. Consequently, when the transistor is biased to invert the channel, the gate is depleted of majority carriers for a certain distance into the gate. Depletion causes an increase in the effective thickness of the gate dielectric, termed the electrical thickness, which in turn deteriorates the performance characteristics of the transistor. For example, an electrical thickness that is as little as 10 percent greater than the physical thickness of the gate dielectric can significantly reduced the strength of the electric field in the channel, thereby reducing the drive current and switching speed of the transistor. The impact of this problem on transistor performance is exacerbated as gate thicknesses are decreased with each technology node.
Metal gates are an attractive alternative to polysilicon gate because metals have a larger supply of charge than doped polysilicon. When a metal gate is inverted, there is no substantial electric field penetration at the interface between the metal gate and gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate dielectric is not increased. The integration of semiconductor transistors having metal gates has been troublesome, however.
It has proven challenging to simply deposit and etch metals to form gate structures. It is also difficult to find etchants and etching conditions where gate metals can be selectively etched without damaging the underlying gate dielectric and substrate. Metal gate deposit-and-etch fabrication schemes are further complicated if two different metals are used to provide dual work function gates. Using a single metal having midrange work function results in gate electrodes with an undesirably high threshold voltage.
Therefore there is need for an improved method to manufacture thin gate layers having a large supply of charge while avoiding the above-mentioned limitations.